1. Field of the Invention
This invention relates to the field of electronic circuits, and in particular to a circuit for generating lower-speed baud rates, such as used for serial communications, from higher-speed oscillators, such as microprocessor clocks
2. Description of Related Art
Digital systems typically include a clocking signal for providing periodic signals, and signals of known duration. That is, the clocking signal provides a time reference upon which other timed actions depend. Within the same system, multiple time references are often required. For example, in a microprocessor system, the microprocessor typically requires a high-speed clock that regulates the speed of the central processing unit (CPU), the speed and timing of memory accesses, and other high-speed events. Additionally, for communicating with external devices, such as modems or printers, the microprocessor requires a relatively low speed clock.
Because whole-cycle frequency dividers are relatively simple devices, compared to frequency generators, systems with multiple time references typically provide the multiple time references by dividing-down a high-speed clock. FIG. 1 illustrates a microprocessor system that includes a conventional frequency divider 100. The divider 100 is programmable to provide a lower speed clock signal, the xe2x80x9cBaud Rate Clockxe2x80x9d, from a higher speed clock signal, the xe2x80x9cXtal Osc Clockxe2x80x9d (Crystal Oscillator Clock). The high-speed clock signal is preferably the highest speed clock within a processing system, which is generally the same clock signal used by the core processor, or CPU, 150. The example divider 100 includes a re-loadable count-down counter 110, and a register 120 that provides the re-load value to the counter 110. In operation, the register 120 is loaded with a value corresponding to a ratio of the high-speed clock frequency to the desired low-speed clock frequency, discussed further below, and thereafter the low-speed clock is automatically generated at the desired frequency, without further intervention by the core processor 150.
The count-down counter 110 is clocked by the higher speed clock signal, and generates an output signal each time the count-down counter 110 reaches zero. The output signal is also coupled to the reload input of the counter 110, and causes the counter 110 to be reloaded with the contents of the register 120 at the next clock cycle of the higher speed clock signal. Thus, if the register 120 contains a value of N, the zero signal will be asserted at each N+1th cycle of the higher speed clock (one cycle to load the value of N, plus N cycles to reduce the count to zero), thereby providing a xe2x80x9cdivide-by-N+1xe2x80x9d frequency divider that can be programmed for a particular division by loading the proper value of N into the register 120. Illustrated in FIG. 1 is a 12-bit register 120 and 12-bit counter 110, thereby allowing the frequency divider 100 to provide a division of the high-speed clock by any integer multiple between 2 and 8192.
Note that unless the high-speed clock is approximately an integer multiple of the low-speed clock, the frequency divider 100 will not be able to provide an accurate low-speed clock frequency. Note also that the higher the ratio of the high-speed to low-speed clock frequencies, the finer the available resolution. Consider, for example, a 100 MHz high-speed clock, and a desired low-speed clock frequency of 18 KHz. A ratio of 5555 provides a low-speed clock of 18,001.8 Hz, and a ratio of 5556 provides a low-speed clock of 17,998.5 Hz. In this example, 5556 would be selected, and the low-speed clock will be within 1.5 Hertz of the desired 18 KHz (less than 0.01% error). Consider, however, a high-speed clock of 100 KHz, and the same desired low-speed clock frequency. A ratio of 5 provides a low-speed clock of 20,000.0 Hz, and a ratio of 6 provides a low-speed clock of 16,666.7 Hz. In this example, the best option (a ratio of 6) will produce an error of over 1,333 Hz. (over 7% error), and would likely be unacceptable. Generally, for acceptable frequency accuracy, a minimum ratio of 50:1 is required for supporting independent high-speed and low-speed clock frequencies. That is, the high-speed clock frequency is typically selected by the designer of the core processor 150, or other components within the microprocessor system, and the low-speed clock frequency is typically determined based on existing communications standards, or based on characteristics of a device that is external to the microprocessor system. As such, the high-speed clock frequency and low-speed clock frequency are generally substantially independent of each other, and an integer-factor relationship between the high-speed and low-speed clocks cannot be assumed. To allow for the programming of an arbitrary low-speed clock frequency, a ratio of 50:1 between the high and low clock frequencies is generally considered a minimum requirement.
This minimum ratio of 50:1 for the general-purpose application of a programmable frequency divider had not been a significant constraint in typical microprocessor designs, because the master CPU clock has conventionally been substantially faster than the clocks required for serial communications, or other derived-clock applications. The increased need for low-power processors (lower processor clock speed), and the increased need for faster communications (higher interfacing clock speeds), however, has substantially narrowed the gap between CPU clock speeds and derived-clock speeds.
It is an object of this invention to provide a frequency divider that can provide accurate low-speed clock frequencies with a minimal difference between the low-speed clock frequency and the clock frequency that provides the input to the frequency divider. It is a further object of this invention to provide a programmable frequency divider that has a resolution that is substantially less dependent upon the difference between the high and low clock frequencies than conventional frequency dividers.
These objects and others are achieved by providing a programmable fractional frequency divider that is configured to enable a finer resolution of output frequency than conventional frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of both an integer divisor as well as a fraction component. The average frequency of the output signal from the fractional divider is dependent upon both the integer divisor and the fraction component, thereby providing for a finer resolution to the average frequency of the output signal. This combination of integer and fractional frequency division is particularly well suited for the generation of signals for systems that are substantially jitter-insensitive.